The present invention relates to a semicustom IC such as a gate array and a standard cell.
FIGS. 6 and 7 illustrate one conventional semicustom IC, wherein FIG. 6 is a plan view and FIG. 7 is a cross-sectional view thereof taken along line Bxe2x80x94B.
As shown in FIGS. 6 and 7, the semicustom IC includes a plurality of basic cells 3a, 3b, . . . , 3n which are densely disposed side by side on a semiconductor substrate 1, wherein a first macrocell 2a is formed using basic cells 3c and 3d and also using interconnection lines in two interconnection layers, a first interconnection layer 7 and a second interconnection layer 9, extending over the basic cells 3c and 3d. 
Furthermore, in this semicustom IC, as shown in FIGS. 6 and 7, ring-shaped power supply lines 4 and 5 for supplying a specific voltage to the first macrocell 2a are formed using interconnection lines in the first interconnection layer 7 and the second interconnection layer 9 extending around the first macrocell 2a. 
In this semicustom IC, as shown in FIGS. 6 and 7, a second macrocell 2b is formed using the basic cell 3a located outside the power supply lines 4 and 5 and also using interconnection lines in the first interconnection layer 7 and the second interconnection layer 9, extending over the basic cell 3a. 
The semicustom IC is described in further detail below. As shown in FIG. 7, an insulating layer 6 is formed on the semiconductor substrate 1 on which the plurality of basic cells 3a, 3b, . . . , 3n are formed. On the insulating layer 6, an interconnection conductor 71 used as a signal interconnection line for the first macrocell 2a is formed in the first interconnection layer 7, and an interconnection conductor 72 used as a signal interconnection line for the second macrocell 2b is formed in the first interconnection layer 7.
In the first macrocell 2a, the basic cells 3c and 3d are electrically connected to the interconnection conductor 71 via connecting conductors (through-hole) 74 extending in the thickness direction through the insulating layer 6. In the second macrocell 2b, the basic cell 3a is electrically connected to the interconnection conductor 72 via connecting conductors 75 extending in the thickness direction through the insulating layer 6.
An insulating layer 8 is formed on the first interconnection layer 7 as shown in FIG. 7. On the insulating layer 8, an interconnection conductor 91 used as a signal interconnection line for the first macrocell 2a is formed in the second interconnection layer 9, and an interconnection conductor 92 used as a signal interconnection line for the second macrocell 2b is formed in the second interconnection layer 9. The interconnection conductor 71 and the interconnection conductor 91 are electrically connected to each other via connecting conductors 94 extending in the thickness direction through the insulating layer 8. Similarly, the interconnection conductor 72 and the interconnection conductor 92 are electrically connected to each other via connecting conductors 95 extending in the thickness direction through the insulating layer 8.
In the conventional semicustom IC constructed in the above-described manner, the first macrocell 2a is formed so as to have a desired function using basic cells 3c and 3d formed on the semiconductor substrate 1 and also using the interconnection conductor 71 in the first interconnection layer 7 and the interconnection conductor 91 in the second interconnection layer 9. Similarly, the second macrocell 2b is formed so as to have a desired function using the basic cell 3a formed on the semiconductor substrate 1 and also using the interconnection conductor 72 in the first interconnection layer 7 and the interconnection conductor 92 in the second interconnection layer 9.
The detailed structures of the power supply lines 4 and 5 are described below with reference to FIGS. 6 and 7.
The power supply line 4 includes an interconnection conductor 41, in the first interconnection layer 7, extending horizontally (in FIG. 6) on the insulating layer 6 and also includes an interconnection conductor 42, in the second interconnection layer 9, extending vertically (in FIG. 6) on the insulating layer 8, wherein the interconnection conductor 41 and the interconnection conductor 42 are connected to each other via a connecting conductor 43 extending in the thickness direction through the insulating layer 8 such that a closed circuit is formed. Similarly, the power supply line 5 includes an interconnection conductor 51, in the first interconnection layer 7, extending horizontally on the insulating layer 6 and also includes an interconnection conductor 52, in the second interconnection layer 9, extending vertically on the insulating layer 8, wherein the interconnection conductor 51 and the interconnection conductor 52 are connected to each other via a connecting conductor 53 extending in the thickness direction through the insulating layer 8 such that a closed circuit is formed.
The first macrocell 2a forms, for example, a memory, and the second macrocell 2b located outside the power supply lines 4 and 5 forms, for example, a battery backup circuit for holding data stored in the memory.
In the case where the memory is formed in the first macrocell 2a of the conventional semicustom IC described above, the battery backup circuit is formed in the second macrocell 2b using the basic cell 3a located outside the power supply lines 4 and 5.
However, in this case, because the second macrocell 2b is formed outside the power supply lines 4 and 5, the space needed to form the second macrocell 2b results in an increase in the total size.
The above problem may be avoided if the basic cell 3b, which is located closest to the first macro cell 2a as shown in FIG. 7, can be used. However, the power supply lines 4 and 5 extending directly above the basic cell 3b make it impossible to use the basic cell 3b for such a purpose.
Aspects of the present invention to provide a semicustom IC which includes a large number of basic cells formed on a semiconductor substrate and which allows a plurality of macro cells to be formed using basic cells in an efficient manner thereby allowing a reduction in the total size of the semicustom IC. The present invention provides a semicustom IC including a plurality of basic cells disposed on a semiconductor substrate, a first macrocell, a second macrocell adjacent to the first macrocell, and a power supply line The first macrocell and second macrocell are each formed using at least one basic cell and a plurality of interconnection layers. The first macrocell is formed using first basic cells of the plurality of basic cells and using interconnection layers disposed over the first basic cells. The power supply line is for supplying power to the first macrocell, and is formed around the first macrocell using an upper interconnection layer of the plurality of interconnection layers. The second macrocell is formed below the power supply line using a basic cell and a lower interconnection layer, extending over the basic cell, of the plurality of interconnection layers.
In other embodiments, the interconnection layers can include three or more interconnection layers.
Because the second macrocell can be formed using the basic cell at the location closest to the first macrocell, the basic cells can be used in an efficient manner, and the total size can be reduced.
In other embodiments, the plurality of interconnection layers can include a total of four interconnection layers and the power supply line is formed using a third interconnection layer and a fourth interconnection layer of the total of four interconnection layers.
In other embodiments, the third and fourth interconnection layers of the total of four interconnection layers can be used to form the power supply line for the first macrocell, and the remaining first and second interconnection layers can be used as interconnection layers for the second macrocell. This allows the second macrocell to be used to form a circuit having a relatively large circuit scale.
In other embodiments, the second macrocell can be an interface circuit disposed between a circuit formed in the first macrocell and another circuit.
This makes it possible to realize a semicustom IC including an interface circuit and reduce the total size of the semicustom IC.
In other embodiments, the first macrocell can form a memory and the second macrocell can form a battery backup circuit for maintaining the content of the memory.
This allows a memory and a battery backup circuit for the memory to be realized using the semicustom IC with a reduced total size.
In other embodiments, the power supply line can partially overlap the first macrocell.
In other embodiments, the interconnection layers can include three or more interconnection layers.
Because a macrocell can be formed using a basic cell at the location closest to the macrocell surrounded by the power supply line, the basic cells can be used in an efficient maimer, and the total size can be reduced.
In other embodiments, the power supply line can be formed such that the power supply line is used in common by at least two macrocells of the plurality of macrocells.
Because the power supply line includes a part which is used in common, the total length of the power supply line is reduced.
In other embodiments, the interconnection layers can include a total of four interconnection layers and the power supply line can be formed using a third interconnection layer and a fourth interconnection layer of the total of four interconnection layers.
The third and fourth interconnection layers of the total of four interconnection layers can be used to form the power supply line, and the remaining first and second interconnection layers can be used as interconnection layers for the macrocell. This allows the macrocell to be used to form a circuit having a relatively large circuit scale.
Aspects of the present invention can also provide a semicustom IC including a plurality of basic cells disposed on a semiconductor substrate, a plurality of macrocells formed using the plurality of basic cells and a plurality of interconnection layers, a first power supply line, and a second power supply line. At least two macrocells of the plurality of macrocells are formed using particular basic cells of the plurality of basic cells and using at least one interconnection layer of the plurality of interconnection layers disposed over the particular basic cells. The first power supply line is for supplying power to one macrocell of the at least two macrocells, and is formed around the one macrocell using an upper interconnection layer of the plurality of interconnection layers. The second power supply line is for supplying power to another macrocell of the at least two macrocells, and is formed around the another macrocell using the upper interconnection layer of the plurality of interconnection layers. The remaining macrocells of the plurality of macrocells are formed using basic cells located below at least one of the first power supply line and the second power supply line and also using a lower interconnection layer of the plurality of interconnection layers .
In other embodiments, the interconnection layers can include three or more interconnection layers.
Because the remaining macrocells of the plurality of macrocells can be formed using the plurality of basic cells at the location closest to the at least two macrocells, the basic cells can be used in an efficient manner, and the total size can be reduced.
In other embodiments, the plurality of interconnection layers can include a total of four interconnection layers and the first power supply line and the second power supply line are formed using a third interconnection layer and a fourth interconnection layer of the total of four interconnection layers.
The third and fourth interconnection layers of the total of four interconnection layers can be used to form the first power supply line for the one macrocell and the second power supply line for the another macrocell. The remaining first and second interconnection layers can be used as interconnection layers for the remaining macrocells of the plurality of macrocells. This allows the remaining macrocells to be used to form a circuit having a relatively large circuit scale.
In other embodiments, the remaining macrocells of the plurality of macrocells can be interface circuits disposed between circuits formed in the at least two macrocells and other circuits.
This makes it possible to realize a semicustom IC including interface circuits and reduce the total size of the semicustom IC.
In other embodiments, the at least two macrocells form memories and the remaining macrocells form battery backup circuits for maintaining the content of the memory.
This can allow memories and battery backup circuits for the memories to be realized using the semicustom IC with a reduced total size.
In other embodiments, the first power supply line and the second power supply line are formed such that the first power supply line and the second power supply line are used in common by more than one macrocell of the plurality of macrocells.
Because the first and second power supply lines include a portion which is used in common, the total length of the first and second power supply lines is reduced.